1. Field of the Invention
The present invention relates to PCI-Express devices and more particularly, to dynamically adjusting data transfer rates for such devices for optimum performance.
2. Background of the Invention
Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect (“PCI”) interface, a local bus standard that uses parallel data transfer, or the extension of PCI known as PCI-X. Both the PCI and PCI-X standard specifications are incorporated herein by reference in their entirety.
More recently, PCI-Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than PCI or PCI-X. PCI-Express is an Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that is compatible with existing PCI cards using the PCI Express bus.
Various other standard interfaces are also used to move data between host systems and peripheral devices. Fibre Channel is one such standard. Fibre Channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols.
Host systems are used in various network applications, including storage area networks (“SANs”). In SANs, plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification) through various controllers/adapters, for example, host bus adapters (“HBAs”).
HBAs (a PCI-Express device) that are placed in SANs receive serial data streams (bit stream), align the serial data and then convert it into parallel data for processing. HBAs operate as a transmitting device as well as the receiving device.
The PCI-Express Specification provides for two categories of lane operating speeds, Generation 1 (Gen 1) rate of 2.5 Ghz and Generation 2 (Gen 2) rate of 5 Ghz. The Gen 2 rate is provided to meet the high data transfer rate of 500 megabytes per second (5 GB). Up to 32 serial lanes can operate in parallel providing a total system transfer rate of 16 gigabytes per second.
The PCI-Express standard merely provides the option for PCI-Express devices to support Gen 1 or Gen 2 speeds, but fails to provide any guidance, as to how the PCI-Express devices should configure themselves to operate in different environments. For example, a host system depending upon its capability may support 4, 8 or any other number of lanes for a HBA. The HBA may have throughput capability of 2 GB, 4 GB or any other throughput rate. The HBA may support 4 lanes, 8 lanes or any other number of lanes depending on the HBA's throughput capability and the data transfer rate. The PCI-Express specification does not provide any guidance as to how this HBA should configure itself so that it can efficiently operate in different environments, as described in the example above.
Therefore, there is a need for a method and system for PCI-Express devices to dynamically adjust data transfer rates depending on the operating environment and HBA capabilities.